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Demonstrated multiple optimizations for the fabrication of stacked silicon nanowire and nanosheet FETs.
December 7, 2017
By: DAVID SAVASTANO
Editor, Ink World Magazine
At this week’s 2017 International Electron Devices Meeting (IEDM), imec reports on multiple key process optimizations for vertically stacked gate-all-around (GAA) silicon nanowire transistors. The optimized CMOS process flow was then used to integrate, for the first time, the GAA nanowire transistors in a functional ring oscillator. This demonstrator shows the promise this technology holds for realizing the sub-5nm technology nodes. Gate-all-around (GAA) MOSFETs based on vertically stacked h...
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